Hello everybody,
Last week the following situation appeared on our MarkV:
<C> core (A4 state):
- BAD EEPROM CSUM
- 3145 DCC ERRORS (number keeps increasing)
- DCC TO RESET
- DEFAULT SYS
<R> core(A4 state)
- 1 DCC errors (constant)
- DEFAULT SYS
<S> core (A7 state), no alarms shown
<T> core (A7 state)
- 1786 DCC errors (constant)
- NO BMS MEM BUFFS
- QST DPM TIMEOUT
Suspecting an issue with the <C> core EEPROM we replaced it, after downloading ALL to C core and R core all the 4 processors went to A7 status and no alarms were shown on the screen.
The day after many diagnostic alarm started coming from the MarkV (although all the 4 cores are still in A7 status) and the LCC screens show the following alarms:
R, S, T core:
- 45 DCC ERRORS
- QST DPM NO DEST
C core: no alarms
Here below some of the diagnostics alarm that keep appearing quite frequently:
- <C> DCC DPM: Invalid destination address
- <C> Sequencing execution overflow
- <C> LCC: Processor rebooted independently
- <Q> COMMON IO communication loss
- <C> DCC BMS: out of memory
- <C> DCC DPM: no BMS memory for isr
- <C> DCC UDM: no BMS memory buffer available
- <C> TCD1 Relays dropped due to IONET failure
In particular the independent reboot of the <C> core occurs in average twice a day or even more and it is for us very concerning.
This MarkV has been running for 20 years with a very few alarms.
For information in this period an upgrade of the DCS is being performed, and the issues came up in concomitance with it.
Can anyone advise which actions should be taken to tackle the issue?
Thank you in advance,
pippo87
Last week the following situation appeared on our MarkV:
<C> core (A4 state):
- BAD EEPROM CSUM
- 3145 DCC ERRORS (number keeps increasing)
- DCC TO RESET
- DEFAULT SYS
<R> core(A4 state)
- 1 DCC errors (constant)
- DEFAULT SYS
<S> core (A7 state), no alarms shown
<T> core (A7 state)
- 1786 DCC errors (constant)
- NO BMS MEM BUFFS
- QST DPM TIMEOUT
Suspecting an issue with the <C> core EEPROM we replaced it, after downloading ALL to C core and R core all the 4 processors went to A7 status and no alarms were shown on the screen.
The day after many diagnostic alarm started coming from the MarkV (although all the 4 cores are still in A7 status) and the LCC screens show the following alarms:
R, S, T core:
- 45 DCC ERRORS
- QST DPM NO DEST
C core: no alarms
Here below some of the diagnostics alarm that keep appearing quite frequently:
- <C> DCC DPM: Invalid destination address
- <C> Sequencing execution overflow
- <C> LCC: Processor rebooted independently
- <Q> COMMON IO communication loss
- <C> DCC BMS: out of memory
- <C> DCC DPM: no BMS memory for isr
- <C> DCC UDM: no BMS memory buffer available
- <C> TCD1 Relays dropped due to IONET failure
In particular the independent reboot of the <C> core occurs in average twice a day or even more and it is for us very concerning.
This MarkV has been running for 20 years with a very few alarms.
For information in this period an upgrade of the DCS is being performed, and the issues came up in concomitance with it.
Can anyone advise which actions should be taken to tackle the issue?
Thank you in advance,
pippo87